The development history of digital isolator

 Analog-to-digital converters (ADC) and digital-to-analog converters (DAC) have existed since the beginning of the digital era. Since the late 1970s and early 1980s, Texas Instruments (TI) took the lead in launching single-chip digital signal processors (DSP), which are needed by engineers to design systems and can easily surpass the effectiveness of analog components.

Early data converters had relatively slow speeds and used parallel interfaces to connect DSPs or processors. With the advancement of process technology, the speed and dynamic range (number of bits) of data converters have also improved, so a faster and wider bus is required.

In today's modern data converters, the conversion rate of Gigasample is much higher than 12 bits per second. When converted into a bus transmission rate, it exceeds 1.5 billion bytes per second. Therefore, when engineers use printed circuit boards to connect DSP, processor, or field-programmable gate array (FPGA), they will encounter challenges. If there are multiple ADCs or DACs in the system, and the analog input or output is in phase, the situation will be more complicated. The parallel bus must match the electronic length and deterministic delay, which is a nightmare for the configuration.

Long before the advent of ultra-high-speed data converters, the industry was aware of this problem. Therefore, the serialized low-voltage differential signal (LVDS) interface was introduced to reduce the number of interconnections. This interface provides LVDS bits to retrieve the data after arranging parallel buses. But because of the relationship between the frequency and the data path, routing is still a problem.

Continuation of the concept of serialization and continuous revision of standards and specifications

However, under this scheme, multiple data converters could be included in a single package and a single frequency. Some applications still used this method to reduce the number of pins. For example, the ADC3445 of Texas Instruments was in a single 48-pin, 8 square cm package, containing four 125-Msample/s, 14-bit ADCs.

By the beginning of the 21st century, the increase in data converter rate obviously caused routing problems. Therefore, the American Electronic Engineering Design and Development Association (JEDEC) launched the JESD204 standard in 2006, continuing the serialized interface concept, using 3.125Gb/s connection rate, and implementing coding and frame processing, thus eliminating the need for additional data frequency. The original standard only provided a single channel and lacked a calibration method. In order to ensure the phase consists of multiple data converters, a common frame frequency was required.

In April 2008, JEDEC launched a revised version A to increase channels for high throughput, but it still needed a common frame frequency to synchronize; in July 2011, a revised version B was launched to increase the line rate to 12.5Gb/s and support deterministic delay (very important for phase consistency), and the internal way of data converter synchronization.

Define the physical interface and provide a larger channel

The JESD204B interface contained one or more high-speed, unidirectional, current mode logic (CML) differential pairs, and the data carrying the data converter was called a "channel." The number of channels was different from the serialized LVDS interface. It did not have to be the same as the number of converters, but it also provided a larger channel for the interface like PCI Express. This was a common misunderstanding when switching to JESD204B.

The other three pins were also important: the device frequency (DEVCLK) was called "frame frequency" in the early modified version, the system reference signal (SYSREF), and the active low sync pin (SYNC). Depending on the device mode, these additional pins can record various times, such as analog conversion, and the movement of data between the data converter and the processing components (Figure 1).

The data converter used DEVCLK to obtain multiple internal frequency signals, such as internal frame frequency used to transmit data, sampling frequency used to record conversion time, and local multiple frame frequency(LMFC) used to establish a deterministic delay. SYSREF was the phase reference signal, which draws LMFC in the sub-category (not used in sub-category zero or sub-category 2); the /SYNC signal can be used for data transmission synchronization of each sub-category, and the LMFC phase reference of sub-category 2.

Establish data format and transmit more stable

Compared with a simple serialized LVDS interface, the model used by JESD204B is similar to a network protocol or an open system interface (OSI). Each layer has different functions. The encoding end performs the functions of each layer sequentially, and the receiving end performs the order Instead, to reconstruct the data.

Each layer performs different functions to make the data of the transmitter and receiver more stable. The JESD204B standard has four layers: transmission, scrambling (not necessary, but recommended), data link, and entity.

The function of the transmission layer is more complicated. The data is grouped in units of 8 bits, and each frame on the transmission side contains multiple 8 bits, while the order on the receiving side is reversed. The 8-bit data converter is quite simple, but other components such as the 11-bit data converter are more complicated. Control bits are also added to the stream to communicate status information to the receiver (Figure 2).

Figure 2 In this case, the transmission layer can connect all layers to counter the response, and implant control bits in the stream to communicate status information to the receiver.

The unnecessary scrambling layer can establish a random data pattern to minimize the noise and related signals in the system. By fixing the polynomial 1 + X^14 + X^15, using the sequence feedback shift register and OR mutex, The encoding and decoding are symmetrical. Under this simple way of signal spectrum expansion, as long as two 8 bytes are received from the link layer, the receiver's descrambler will be locked. Although this function is not necessary, it is quite helpful for the purity of the spectrum. 

The data link layer is responsible for 8b/10b encoding, which converts between 8-byte and 10-bit standard symbols. This layer is also responsible for establishing working links, including frame and channel calibration. Several standard 8b/10b symbols are reserved for this. And monitor the connection physique. The encoding also includes a 20% overhead penalty, and future versions may move to higher-level encodings such as 64/66b to regain the lost bandwidth in the interface.

The physical layer is purely the driver and receiver, moving bit and frequency data recovery (CDR) circuit, the physical interface uses alternating current (AC) to couple the CML driver and receiver, 8b/10b encoding provides direct current (DC) average, and avoids AC coupling Baseline drift occurs; encoding also provides enough edge transition for CDR to quickly lock data when establishing a link.

All in all, when the data converter establishes a link with the processing component, these four layers are used, and the data controller data and control information is stably transmitted from the transmitter to the receiver.

In order to achieve backward compatibility, JEDEC established the concept of "subcategories" to allow the interface to be applied to various operating modes. Subcategory zero is a mode compatible with the revised version of A but also supports a 12.5Gb/s channel rate. This model is compatible with The A revised version is the same, supports multiple synchronous data converters, but does not support deterministic delay.

Create subcategories and achieve backward compatibility

The delay between data converters may be fixed, but it will still change at startup. Therefore, system designers must provide solutions to determine when the data from individual data converters will arrive at the FPGA or processor, and this mode does not use SYSREF. Sub-category one provides deterministic delay and synchronization of internal multiple devices while using an internal frame, local multiple frame frequencies, and SYSREF frequency signals. When the symbols of the data converter and the processing component are transmitted serially, the internal frame frequency is used, and the LMFC provides a reference for the known delay.

The phase of the DEVCLK plus the SYSREF signal determines the internal frame frequency and LMFC. Because in this mode, DEVCLK and SYSREF are closely related, SYSREF must be synchronized with the device frequency, thereby limiting the configuration so that the two signals can match, but because the subcategory is zero In the SYNC signal, so the data channel does not need to match.

In sub-category 2, the internal frame frequency of each device is the same as LMFC, which is no different from sub-category 1, but at this time, SYNC signal is required to achieve synchronization and deterministic delay. In this mode, the phase of the SYNC signal can be calibrated internally The frame frequency is synchronized with LMFC and must be source-synchronized with DEVCLK. Due to the strict time requirements of DEVCLK and /SYNC, this mode is not recommended for extremely high sampling rates.

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