Multi-channel intermediate frequency digital direct-spread communication system based on AD6623

Spread spectrum communication has the advantages of anti-interference, anti-multipath, and low probability of interception. Since the 1970s, the theory and methods of spread spectrum communication have been greatly developed. Direct Sequence Spread Spectrum (Direct Spread Spectrum), as a common method of spread spectrum communication, has been successfully applied to military and civilian communications and has become one of the core technologies of the third-generation mobile communication system, fully demonstrating its significant advantages and strong vitality.

Spread spectrum communication comes at the expense of increasing the bandwidth of information transmission. However, the existing frequency band resources are very limited. In order to increase the rate of information transmission within bandwidth per unit, the idea of ​​using direct sequence spread spectrum CDMA is proposed. At the sending end, one serial data information is converted into N parallel data information through serial/parallel conversion, and then each channel of information is modulated with N mutually orthogonal PN codes to spread spectrum, forming baseband information spread N channels spectrum. Each channel of baseband information is subjected to baseband shaping and filtering, up-conversion modulated to the same intermediate frequency, and then N channels of signals are synthesized and sent to the radio frequency interface to complete the transmission. At the receiving end, the same N PN codes as the transmitting end are used to perform cross-correlation calculations with the received signal and then compare with the decision threshold to obtain synchronization information, compare the cross-correlation value to obtain user data, and parallelly/ serially convert the restored N channels data. Therefore, The transmission bandwidth required by the entire system will be reduced to 1/N of the original.

The A/D converter adopts AD6644 of AD company, which has a maximum sampling rate of 65MSPS and a resolution of 14 bits. In this system, the 6MHz intermediate frequency signal is directly over-sampled by AD6644 to realize the digitization of the intermediate frequency of the system. The sampling clock is 19.6608MHz.

The digital down-converter uses AD6620 of AD company, which is a high-performance digital signal processing chip launched by the American AD company. It can complete the down-conversion and decimation filtering of high-speed digital signals with powerful functions. The internal signal processing unit consists of four parts: a frequency converter, a second-order fixed coefficient comb decimation filter (CIC2), a fifth-order fixed coefficient comb decimation filter (CIC5), and a coefficient programmable decimation filter (RCF) ). In this system, the initialization of the AD6620 is completed by the DSP TMS320LC31, and the AD6620 outputs the processed baseband data to the DSP through the parallel port.

The D/A converter adopts AD9772A of AD company, its highest conversion rate is 160MHz, and the conversion number is 14 bits. In this system, AD9772A completes the conversion of the multiplexed digital intermediate frequency of the transmitting unit to the analog intermediate frequency, and the conversion clock frequency is 19.6608MHz.

The digital up-converter adopts the AD6623 of AD company. Its main features are as follows: up to 104MHz working clock, monolithic integration of four independent digital transmitting channels, programmable interpolation filter and gain control. The signal processing inside AD6623 includes the following four parts: frequency converter, second-order reinterpolation cascaded integrator comb filter (rCIC2), fifth-order interpolated cascaded integrator comb filter (CIC5), and a RAM coefficient filter ( RCF). In this system, a total of four AD6623 chips are used to form 16 direct sequence spread spectrum transmitting units. Each channel obtains spread spectrum baseband information from the FPGA, performs baseband shaping and filtering, interpolation, and upconversion modulation to an intermediate frequency of 6MHz. Finally, 16 channels of intermediate frequency modulated signal are synthesized into one channel, and then sent to the radio frequency transmitting unit interface after D/A conversion.

DSP adopts TMS320LC31 of TI Company. TMS320LC31 uses an improved Harvard structure, which is a digital signal processing chip capable of floating-point operations, with the main frequency of up to 60MHz. In this system, the main function of TMS320LC31 is: in the transmission process, the simulated baseband information is generated by the program. When the DSP detects the interrupt signal of the application data generated by the FPGA, the simulated baseband information is sent to the FPGA through the data bus; In the receiving process, the DSP receives each channel of data that has been despread through the interrupt signal generated by the FPGA, completes the demodulation of each channel of information, and performs parallel-serial conversion of the demodulated information to serial information in the transmission time. In addition, the DSP is responsible for completing the initialization of the AD6623 and AD6620 and is also responsible for the carrier recovery of the AD6620 during operation.

What FPGA adopts is EP1S40B956C7 of ALTERA Company, it contains 41250 logic units inside, the usable I/O pin is 683, the speed is 0.7ns, can fully meet the various performance requirements of the system. In the transmission process of this system, the FPGA sends an interrupt request to the DSP to obtain the baseband information to be sent. In FPGA, one serial baseband information is converted into 16 parallel baseband information, and 16 mutually orthogonal PN codes are respectively multiplied to complete the spread spectrum, and then respectively sent to the 16 data channels of four AD6623. In the receiving process, the digital downconverter AD6620 sends the down-converted and filtered baseband data to the FPGA, which is matched with 16 local orthogonal PNs to complete the capture and tracking of 16 channels of PN codes, thereby realizing the despread of 16 channels of data. Expand. Finally, FPGA sends an interrupt to the DSP, and the DSP completes the assembly and restoration of 16-channel data.